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74LVC823A 9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
Product specification 1998 Sep 24
Philips Semiconductors
Philips Semiconductors
Product specification
9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC823A
DESCRIPTION FEATURES
* 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic * Supply voltage range of 2.7V to 3.6V * Complies with JEDEC standard no. 8-1A * Inputs accept voltages up to 5.5V * CMOS low power consumption * Direct interface with TTL levels * 9-bit positive edge-triggered register * Independent register and 3-State buffer operation * Flow-through pin-out architecture
The 74LVC823A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-state operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC823A is a 9-bit D-type flip-flop with common clock (CP), Clock Enable (CE), Master Reset (MR) and 3-State outputs for bus-oriented applications. The nine flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition provided CE is LOW. When CE is HIGH the flip-flops hold their data. A LOW on MR resets all flip-flops. When OE is LOW, the contents of the nine flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf 2.5 ns SYMBOL PARAMETER Propagation delay CP to Qn Propagation delay MR to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Notes 1 and 2 CONDITIONS CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V TYPICAL 5.1 5.2 150 5.0 27 UNIT ns ns MHz pF pF
tPHL/tPLH
fmax CI CPD
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi ) (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 24-Pin Plastic SO 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C ORDERING CODE 74LVC823A D 74LVC823A DB 74LVC823A PW PKG. DWG. # SOT137-1 SOT340-1 SOT355-1
1998 Sep 24
2
853-2124 20078
Philips Semiconductors
Product specification
9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC823A
PIN DESCRIPTION
PIN NUMBER 1 2, 3, 4, 5, 6, 7, 8, 9, 10 11 12 13 14 23, 22, 21, 20, 19, 18, 17, 16, 15 24 SYMBOL OE D0 to D8 MR GND CP CE Q0 to Q8 VCC NAME AND FUNCTION Output enable input (active LOW) Data inputs Master reset (active LOW) Ground (0 V) Clock pulse (active rising) Clock enable (active LOW) 3-State flip-flop outputs Positive supply voltage
FUNCTION TABLE
INPUTS OPERATING MODES Clear Load and read register Load register and disable outputs Hold OE L L L H H L MR L H H H H H CE X L L L L H CP X X X NC Dn X l h l h X INTERNAL FLIP FLOPS FLIP-FLOPS L L H L H NC OUTPUTS Q0 to Q8 L L H Z Z NC
H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition Z = high impedance OFF-state = LOW-to-HIGH clock transition NC= no change
PIN CONFIGURATION
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 MR GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 V CC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 CE CP
LOGIC SYMBOL
11 1
2 3 4 5 6 7 8 9 10
D0 D1 D2 D3 D4 D5 D6 D7 D8
MR
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
23 22 21 20 19 18 17 16 15
CP
CE
SA00418
13
14
SA00419
1998 Sep 24
3
Philips Semiconductors
Product specification
9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC823A
LOGIC SYMBOL (IEEE/IEC)
1 11 14 13
FUNCTIONAL DIAGRAM
2 3 4 5 6 D0 D1 D2 D3 D4 D5 D6 D7 D8 CP CE MR OE FF0 to FF8 3-STATE OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 23 22 21 20 19 18 17 16 15
EN R G1 1C2
2
2D
23 7 22 21 20 19 13 18 17 16 1 15 14 11 8 9 10
3 4 5 6 7 8 9 10
SA00420
SA00421
LOGIC DIAGRAM
D0 MR D1 D2 D3 D4 D5 D6 D7 D8
D
R
Q
D
R
Q
D
R
Q
D
R
Q
D
R
Q
D
R
Q
D
R
Q
D
R
Q
D
R
Q
CP CE FF0
CP FF1
CP FF2
CP FF3
CP FF4
CP FF5
CP FF6
CP FF7
CP FF8
CP OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
SA00422
1998 Sep 24
4
Philips Semiconductors
Product specification
9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC823A
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL PARAMETER DC supply voltage (for max. speed performance) VCC VI VO Tamb tr, tf DC supply voltage (for low-voltage applications) DC Input voltage range DC output voltage range; output HIGH or LOW state DC output voltage range; output 3-State Operating ambient temperature range in free-air Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS MIN 2.7 1.2 0 0 0 -40 0 0 MAX 3.6 V 3.6 5.5 VCC 5.5 +85 20 10 C ns/V V V UNIT
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output HIGH or LOW state DC output voltage; output 3-State DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI t0 Note 2 VO uVCC or VO t 0 Note 2 Note 2 VO = 0 to VCC CONDITIONS RATING -0.5 to +6.5 -50 -0.5 to +6.5 "50 -0.5 to VCC +0.5 -0.5 to 6.5 "50 "100 -65 to +150 500 500 UNIT V mA V mA V mA mA C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Sep 24
5
Philips Semiconductors
Product specification
9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC823A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = -12mA VO OH HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = -100A VCC = 3.0V; VI = VIH or VIL; IO = -18mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 24mA II IOZ Ioff ICC ICC Input leakage current 3-State output OFF-state current Power off leakage supply Quiescent supply current Additional quiescent supply current per input pin VCC = 3 6V; VI = 5 5V or GND 3.6V; 5.5V VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND VCC = 0.0V; VI or VO = 5.5V VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 "0.1 "0 1 0.1 0.1 0.1 5 VCC*0.5 VCC*0.2 VCC*0.6 VCC*0.8 0.40 0.20 0.55 "5 "5 "10 10 500 A A A A A V VCC V VCC 2.0 GND V 0.8 TYP1 MAX V UNIT
VIL
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
1998 Sep 24
6
Philips Semiconductors
Product specification
9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC823A
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tW tW tSU tSU trem th th fmax PARAMETER Propagation delay CP to Qn Propagation delay MR to Qn 3-State output enable time OE to Qn 3-State output disable time OE to Qn Clock pulse width HIGH or LOW Master Reset pulse width HIGH or LOW Setup time Dn to CP Setup time CE low before CP Removal time MR Hold time HIGH or LOW Dn after CP Hold time CE LOW before CP Maximum clock pulse frequency WAVEFORM VCC = 3.3V 0.3V MIN Figures 1, 4 Figures 1, 4 Figures 2, 4 Figures 2, 4 Figure 1 Figure 1 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 1 1.5 1.5 1.5 1.5 3.3 3.3 1.3 1.8 1.0 2.0 1.3 150 200 TYP1 5.1 5.2 5.2 3.8 MAX 8.0 7.9 7.65 6.0 VCC = 2.7V MIN 1.5 1.5 1.5 1.5 3.3 3.3 1.8 1.0 2.0 2.0 1.3 150 MAX 8.9 8.8 8.65 7.1 ns ns ns ns ns ns ns ns ns ns ns MHz UNIT
NOTE: 1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25C.
1998 Sep 24
7
Philips Semiconductors
Product specification
9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC823A
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH -0.3V at VCC w 2.7V; VY = VOH - 0.1 VCC at VCC t 2.7V
VI CP INPUT GND VM tsu th VI Dn,CE INPUT 1/fmax VI CP INPUT GND VM tW tPHL VOH QnOUTPUT VOL VM tPLH GND VOH Qn OUTPUT VOL tsu th
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 3. Data setup and hold times for the Dn input and CE input to the CP input.
SA00423
Figure 1. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency.
CP INPUT trem MR INPUT tw
VI OE INPUT GND tPLZ V CC OUTPUT LOW-to-OFF OFF-to-LOW VOL t PHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled PULSE GENERATOR VI D.U.T. RT CL 50pF 500 VO 500 VM VX tPZH tPZL Qn OUTPUT VM tPHL
Figure 4. Master reset pulse width, master reset to clock removal time, master reset to output propagation delay.
VY VM
TEST CIRCUIT
VCC S1 2 x VCC Open GND
SA00424
Figure 2. 3-State enable and disable times.
Test VCC t 2.7V 2.7V - 3.6V VI VCC 2.7V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
Figure 5. Load circuitry for switching times.
1998 Sep 24
8
EEEEEEEEEEE EEEEEEEEEEE
VM VM
SA00425
SA00519
SY00003
Philips Semiconductors
Product specification
9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC823A
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
1998 Sep 24
9
Philips Semiconductors
Product specification
9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC823A
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
1998 Sep 24
10
Philips Semiconductors
Product specification
9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC823A
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
1998 Sep 24
11
Philips Semiconductors
Product specification
9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC823A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 08-98 9397-750-04583
Philips Semiconductors
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